Technical Field
The disclosure relates to a multi-tasking system in which several data producing tasks may send messages to a consumer element asynchronously. The disclosure relates more particularly to a queue structure configured to sort the messages so that the consumer element may process them sequentially according to its availability.
Description of the Related Art
FIG. 1A is a block diagram of an exemplary multiprocessor system. The system may include several processors P0, P1 . . . Pn, a shared memory SMEM and a peripheral device 10, connected together by an interconnecting device CONN, for instance a bus.
The device 10 may be a consumer element, for example a network interface, a mass storage interface, a graphical user interface, etc. The consumer device may receive data generated by one or more processors. Such a device may typically handle multiple data streams and offer several types of processing. Thus, the data is provided to device 10 together with processing parameters. The parameters may be provided in the form of “messages.” A message may contain the data to be processed or identify a slot in the memory SMEM. Where the peripheral device manages DMA (“Direct Memory Access”) transfers with memory SMEM, messages may only contain the parameters of the transfer.
The consumer device 10 includes a core hardware intellectual property HWIP block that processes the messages. This core is usually designed to process messages asynchronously, and cannot absorb a burst of messages sent by multiple processors. The device 10 includes a write queue 12 where the messages of the burst are stored until the core HWIP can process them.
In this context, the designer faces the recurrent difficulty of sizing the hardware write queue 12. If the queue is too shallow, data producer elements (processors) often stall to wait for slots to be freed in the queue. If processor stalls are to be avoided altogether, the queue depth may reach such a large value that the queue occupies an unreasonable surface area on the circuit. This difficulty is exacerbated when the messages are of variable size.
To push back the stalling limits of data producing processors while using a shallow hardware queue, U.S. Pat. No. 8,606,976 to Desoli et al. proposes a mechanism where the queue may overflow into the system memory; into a software managed queue. The overflow is performed in a reserved memory area of fixed size. This solution pushes back the stalling limit for the production of data, but does not eliminate it. The reserved memory area, whether used or not, is permanently removed from the available space for other applications in the system memory.